This invention relates to a semiconductor device, an interposer for a semiconductor device and a method for manufacturing the same, and more particularly to, a semiconductor device including a semiconductor chip, an interposer to be used as a substrate or a lead frame for mounting a semiconductor chip and a method for manufacturing the same.
A conventional semiconductor device having a ball grid array (BGA) packaging comprises a substrate, a semiconductor chip (IC, LSI chip) mounted on the surface of the substrate, first wiring patterns formed around the chip, each of which is connected to each pad on the chip by a bonding wire, second wiring patterns formed on the back side of the substrate, throughholes having a plating on the inner surfaces thereof for connecting the first wiring pattern to the corresponding second wiring pattern, and solder balls for connecting the second wiring pattern to an input-output wiring pattern formed on a circuit board by a reflow solder. All parts mounted or formed on the surface of the substrate are covered by a molding resin.
Similar conventional devices and methods for manufacturing the same are known by many publications. For example, Japanese Published Patent Application No. 3-94459 discloses a semiconductor chip module comprising a die-bonding pad and a bonding pad having a non-etching metal layer, such as a gold plating, formed on a metal plate base, and a method for manufacturing the same. Japanese Published Utility-model Application No. 63-3160 discloses an integrated circuit device comprising a lead frame protruding from the back side of a resin package, and a heat-resisting insulating tape disposed on the the same side thereof. Japanese Published Patent Application No. 5-63109discloses a molded IC package comprising a contact hole formed inside a resin for conducting a inner lead to the surface or back side of a package, and a conductive filler filled into the contact hole so as to be used as an input-output contact. Japanese Published Patent Application No. 5-283460 discloses a semiconductor device comprising a semiconductor chip mounted on a insulating base-film on which a lead pattern is formed, and a bump connected to the lead pattern and exposed from the base-film. Japanese Published Patent Application No. 6-112354 discloses a thin over-molded semiconductor device comprising a semiconductor die mounted on a substrate having a conductive layer, and a solder ball connected to the conductive layer and exposed from the substrate, and a method for manufacturing the same. Japanese Published Patent Application No. 6-216276 discloses a semiconductor device comprising a wiring pattern formed on a substrate so that a plane thereof is higher than that of a substrate on which a semiconductor chip is mounted, and a throughhole, wherein the inner and outer ends of the wiring pattern is connected to the semiconductor chip and the throughhole, respectively, and a solder bump is connected to an exposed portion of the throughhole. Japanese Published Patent Application No. 5-144995 discloses a semiconductor package comprising a package substrate having a throughhole, and a metal ball interposed between the lower end of the throughhole and an input-output pattern on a circuit board. Japanese Published Patent Application No. 5-211202 discloses a composite flip-chip semiconductor device comprising a interposer having a plurality of conducting paths provided on both side of a substrate and a conductive trace for connecting the paths formed on the surface of the substrate, and a metal ball for connecting a flip-chip semiconductor device, and a method for manufacturing the same. Japanese Published Patent Application No. 3-269962 discloses a connecting member comprising a pair of resin holder for holding a conductive member in a manner that the conducting member protrudes from the resin holder, wherein the surface of the conductive member is coated by a solder.
In the conventional semiconductor devices, however, there are disadvantages as described below;
(a) the device disclosed in Japanese Published Patent Application No. 3-94459 comprises a large number of parts, hence resulting in increased cost for materials and increased assembly costs.
(b) the effective inductance is increased because the length of a wiring pattern is long. Therefore, crosstalk noise increases correspondingly and high-speed transmission characteristics become worse in signal transmission.
(c) fatigue failure due to thermal stress in heat cycle is likely to occur because there are a lot of wiring contacts in the device.
(d) additionally, reliability decreases because the throughholes and solder balls themselves are subject to fatique failure.